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Texas Instruments /MSP432P401Y /CS /CSSETIFG

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Interpret as CSSETIFG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SET_LFXTIFG_0)SET_LFXTIFG 0 (SET_HFXTIFG_0)SET_HFXTIFG 0 (SET_HFXT2IFG_0)SET_HFXT2IFG 0 (SET_DCOR_OPNIFG_0)SET_DCOR_OPNIFG 0 (SET_FCNTLFIFG_0)SET_FCNTLFIFG 0 (SET_FCNTHFIFG_0)SET_FCNTHFIFG 0 (SET_FCNTHF2IFG_0)SET_FCNTHF2IFG 0 (SET_PLLOOLIFG_0)SET_PLLOOLIFG 0 (SET_PLLLOSIFG_0)SET_PLLLOSIFG 0 (SET_PLLOORIFG_0)SET_PLLOORIFG 0 (SET_CALIFG_0)SET_CALIFG

SET_HFXTIFG=SET_HFXTIFG_0, SET_FCNTHF2IFG=SET_FCNTHF2IFG_0, SET_LFXTIFG=SET_LFXTIFG_0, SET_HFXT2IFG=SET_HFXT2IFG_0, SET_PLLLOSIFG=SET_PLLLOSIFG_0, SET_CALIFG=SET_CALIFG_0, SET_PLLOORIFG=SET_PLLOORIFG_0, SET_DCOR_OPNIFG=SET_DCOR_OPNIFG_0, SET_PLLOOLIFG=SET_PLLOOLIFG_0, SET_FCNTHFIFG=SET_FCNTHFIFG_0, SET_FCNTLFIFG=SET_FCNTLFIFG_0

Description

Set Interrupt Flag Register

Fields

SET_LFXTIFG

Set LFXT oscillator fault interrupt flag

0 (SET_LFXTIFG_0): No effect

1 (SET_LFXTIFG_1): Set pending interrupt flag
SET_HFXTIFG

Set HFXT oscillator fault interrupt flag

0 (SET_HFXTIFG_0): No effect

1 (SET_HFXTIFG_1): Set pending interrupt flag
SET_HFXT2IFG

Set HFXT2 oscillator fault interrupt flag

0 (SET_HFXT2IFG_0): No effect

1 (SET_HFXT2IFG_1): Set pending interrupt flag
SET_DCOR_OPNIFG

Set DCO external resistor open circuit fault interrupt flag.

0 (SET_DCOR_OPNIFG_0): No effect

1 (SET_DCOR_OPNIFG_1): Set pending interrupt flag
SET_FCNTLFIFG

Start fault counter set interrupt flag LFXT

0 (SET_FCNTLFIFG_0): No effect

1 (SET_FCNTLFIFG_1): Set pending interrupt flag
SET_FCNTHFIFG

Start fault counter set interrupt flag HFXT

0 (SET_FCNTHFIFG_0): No effect

1 (SET_FCNTHFIFG_1): Set pending interrupt flag
SET_FCNTHF2IFG

Start fault counter set interrupt flag HFXT2

0 (SET_FCNTHF2IFG_0): No effect

1 (SET_FCNTHF2IFG_1): Set pending interrupt flag
SET_PLLOOLIFG

PLL out-of-lock set interrupt flag

0 (SET_PLLOOLIFG_0): No effect

1 (SET_PLLOOLIFG_1): Set pending interrupt flag
SET_PLLLOSIFG

PLL loss-of-signal set interrupt flag

0 (SET_PLLLOSIFG_0): No effect

1 (SET_PLLLOSIFG_1): Set pending interrupt flag
SET_PLLOORIFG

PLL out-of-range set interrupt flag

0 (SET_PLLOORIFG_0): No effect

1 (SET_PLLOORIFG_1): Set pending interrupt flag
SET_CALIFG

REFCNT period counter set interrupt flag

0 (SET_CALIFG_0): No effect

1 (SET_CALIFG_1): Set pending interrupt flag

Links

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Register License

Copyright © 2012-2018 Texas Instruments Incorporated - http://www.ti.com/

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.

Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

Neither the name of Texas Instruments Incorporated nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data